The semiconductor industry has experienced rapid growth due to improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from shrinking the semiconductor process node (e.g., shrinking the process node towards the sub-20 nm node). As device dimensions shrink, voltage nodes also shrink, with modern core device voltages trending toward less than 1 Volt, and input/output (I/O) device voltages under 2 Volts.
A semiconductor process node can be specified by size (for example 40 nm, 28 nm, 16 nm, etc.), where a smaller size has a higher gate density and denotes a more advanced process node. A given process node typically specifies parameters of its core devices and one or more types of I/O devices. The core devices and I/O devices are characterized by parameters such as maximum power and ground voltage levels, maximum load current, gate density, speed, etc.
There can be further differences between process nodes of a give size (e.g., 20 nm), such as various process nodes adapted for low power (LP), high performance (HP), a low power with high-k metal gates (HPL) or high performance for mobile applications (HPM), for example. While a more advanced process node may have many important advantages, such as speed and size, those advances can come with challenges. For example, as the process node becomes more advanced, circuit design may have to account for one or more challenges, such as reduced reliability, gates and interconnections with a lower maximum load current due to electromigration (“EM”) concerns, increased sensitivity to electrostatic discharge, and/or increased leakage, for example. In some approaches, resistor EM may degrade by about 0.1 mA/μm from a mature process node to a more advanced process node, such as a process node with a higher gate density.
In common electronic devices, higher power components such as analog or radiofrequency (“RF”) circuits typically interface with a higher density integrated circuit located on a separate wafer. The wafer can have logic circuitry that forms a high speed digital circuit, such as digital logic for a microprocessor, a standard cell, SRAM or digital phase locked loop (PLL), for example. This logic circuitry is typically implemented using core devices. An input/output (“I/O”) circuit on the wafer is typically used to couple signals between the logic circuitry (also referred to herein simply as logic) and electronic components external to the wafer, such as the analog or RF circuits mentioned above. As is known, I/O circuits perform their function using I/O circuitry, including primitives such as: a level-shifter circuit, a pre-driver circuit, a post-driver circuit, a receiver circuit, an electrostatic discharge protection circuit (“ESD”), etc. The I/O circuitry is typically implemented using transistors of one of the I/O device types specified for the process node used.
In one approach, the logic and I/O circuit are disposed on a substrate, with the logic centrally located on the wafer. Outward of the logic is the receiver, pre-driver, and level shifter circuits. Outward of those components is the post-driver and ESD protection circuit. Disposed on top of the post-driver and ESD protection circuit are pads for electrical connection to components external to the wafer. The wafer is implemented at a particular process node.
It can be desirable to improve a given logic circuit by using a more advanced process node for a wafer, for example a node having a higher gate density. Generally, however, using a more advanced process node does not improve the I/O circuit to the same extent as the logic. If the advanced process node has reduced EM or ESD resilience compared to a more mature process node, for example, that will constrain the shrink factor of the post-driver and ESD protection circuit when attempting to implement those circuits on the more advanced process node. To provide the requisite protections for electrostatic discharge and EM, it can be necessary to change the architecture of the post-driver and ESD protection circuits.